1. Field of the Invention
Embodiments of the present invention generally relate to the design of a processor in a computer system. More specifically, embodiments of the present invention facilitate merging stores in a store queue in a processor that supports checkpointing.
2. Related Art
Most modern processors include store queues to prevent the processor from experiencing delays associated with committing stores to the next level of the memory hierarchy. Generally, when a store is executed by a processor the store is buffered in a store queue, making it appear that the store has been completed. However, the store may be held in the store queue until other accesses to the next level of the memory hierarchy have finished.
Because a store can be held in the store queue for an extended period of time, processors typically forward data from buffered stores to subsequent dependent loads so that the loads can proceed without waiting for the buffered stores to complete. In order to determine if data should be forwarded to a subsequent load, processors compare the addresses of subsequent loads to the address for each entry in the store queue. This process typically involves using a content addressable memory (CAM) circuit to perform the comparison. Unfortunately, CAM circuits require considerable semiconductor area, consume significant power, and complicate the processor's design. Moreover, because the size of the CAM circuit scales with the number of entries in the store queue, the designers have been forced to limit the number of entries in the store queue.
Hence, what is needed is a store queue without the above-described problems.